Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Using Timequest to Analyze Processor Bus Interface

We have a design with a processor connected to the FPGA using standard address, data and control signals. This processor uses an internal clock of 200 MHz to control these signals and we have a 200 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

--- Quote Start ---

Chip select, rd/wr strobe

--- Quote End ---

indeed not too much to work with.