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Altera_Forum
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7 years ago

Using Timequest to Analyze Processor Bus Interface

We have a design with a processor connected to the FPGA using standard address, data and control signals. This processor uses an internal clock of 200 MHz to control these signals and we have a 200 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi Kaz,

Thanks for the response but I was hoping this wouldn't be the answer. I presume that in your description above, we need standard 2 flop synchronizer for address and data. I was thinking that maybe a pipelined compare and decode might do the trick for address but that might still be susceptible to metastability. Thoughts?