Honored Contributor
Honored ContributorOk, I got it running now after some extensive trial and error, I found out the address of the Descriptor Read and Write master was in 32 Bit words so I had to divide it by 4 so the descitptor fields are not at address 0 , 4, 8 ... 28 they are at 1, 2 .... and the source address in the desciptor must be byte aligned.
I also had to enable byte reordering on the sgdma to get the correct pixel data out of the dc_fifo. BUT I do not understand the burstcount signal of the SGDMA, what is it for? It is set to 4, chaning this to 8 does not do anything, changing it to 2 and the transfer takes longer time. BTW it takes about 2000 clocks at 100MHz to get the 1600 bytes for one line out of the sdram via the sgdma, datawidth is 32 bit, (sdram is also at 100 MHz clock phase -54 deg) . I thought it would be faster!!! If I change the datawidth of the sgdma to 16 bit like the sdram datawidth, it takes longer time for the datatransfer. I see in the sopc generator output that the sdram controller has a burstcount signal with a width of 0, so how can burst be used at all? If I disable burst transfer on the sgdma the tranfer does take longer time. One other problem is when write to the sdram to fill / clear the framebuffer, I see several pixels per line which do not get written correctly to the sdram or are not read back correctly. It looks like an uninitialised ram cell (random color). the following is the code I use to clear / write the framebuffer (doublebuffer):-- clear buffer
clearscreen : process
begin
wait until rising_edge(clock_clk);
if (reset_reset = '1') then
clearcounter <= 0;
sdram_master_write <= '0';
clearscreen_finished <= '0';
else
if (clearscreen_finished = '0') then
if (clearcounter < (frameHeight * frameWidth * 2)) then
if (sdram_lock_required = '0') then
if (sdram_master_waitrequest = '0') then
sdram_master_address <= sdram_master_address <= std_logic_vector(to_unsigned(SDRAMbase + (clearcounter / 2), 32));
if (clearcounter < (frameHeight * frameWidth)) then
sdram_master_writedata <= "0000100000000000" & clearcolor;
else
sdram_master_writedata <= "00000000001000000000000000100000"; -- g
end if;
sdram_master_byteenable <= "1111";
sdram_master_write <= '1';
clearcounter <= clearcounter + 2;
end if;
else
if (sdram_master_waitrequest = '0') then
sdram_master_write <= '0';
end if;
end if;
else
if (sdram_master_waitrequest = '0') then
sdram_master_write <= '0';
clearscreen_finished <= '1';
end if;
end if;
end if;
end if;
end process clearscreen;
