Honored Contributor
Honored ContributorI just looked at the schematic and it looks like they use a similar JTAG scheme as the Altera SoC dev kit. There is a "USB disable" that is issued when you plug the external programming cable up to the JTAG header. This iscolates the embedded USB blaster on the board so that you can use the header instead. Normally I would say to make sure you don't have the embedded onboard blaster connected at the same time since I don't know how the board will react but it sounds like you have that covered :)
I was looking at their rev C schematic (page 11): http://www.rocketboards.org/pub/documentation/arrowsockitevaluationboard/c5s_rev_c_05_07_13.pdf Pin 2 of a external USB blaster is ground so when you connect to the header you pull the USB_DISABLE_n signal low which lets the CPLD know you have something else driving the JTAG chain.
