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but I'm aware that clock delay may become a problem if I don't distribute the signal appropriately.
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You can expect, that Quartus will assign global clock resources automatically, if appropriate. You usually don't care for this low level details. The delay between clk and half_clk will exist anyway, and possibly cause problems for signals crossing between both clock domains. Quartus timing analyzer will you inform about it, however.
The regular suggestion is to avoid clock dividers for internal clock signals and use divided clock enable signals instead.
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how you interface your MaxII with the memory which is store the configuration of FPGA
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Other than most FPGA, MAXII has internal non-volatile configuration memory.
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