Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Using System Verilog Assertions

Hello, I've seen a few books on System Verilog Verification using assertions and was wondering if many people are using assertions in their FPGA development? My co-worker says it can be a lot of typi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks Ben for the plug-ins to cvcblr.com Recently I presented at FPGACamp Bangalore evnt on SystemVerilog for FPGA design & verification, see:

Search in Google for "FPGACamp Bangalore systemverilog" (Am unable to post URL links in this forum as of now)

I will be glad to share the slides, contact us via cvcblr.com (About Us page has a contact form).

IN Bangalore we have successfully trained several FPGA engineers to adopt modern design & verification methodologies using PSL/SystemVerilog Assertions and even VMM. We have seen that Active-HDL fits their bill smoothly to explore SVA/PSL Recently Mentor released their DE version with similar features. So you have multiple choice!

Regards

Srini

cvcblr.com/blog