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Thanks Ben! I had the same thoughts; it is just a matter of convincing my co-workers to adopt the practice of using assertions and other verification tools.
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A few comments:
1. assertion-based verification should be adopted by all involved in the design and verification process. Having partial adoption weakens the process.
2. I put the 1st ten pages of our book at
systemverilog.us/abv_pg1to10.pdf It explains why assertion-based verification is very important.
3. I now have an Indian edition on our SystemVerilog Assertions Handbook, 2nd Edition book available through Srinivasan Venkataramanan. Contact him at
cvcblr.com Srini also provides training and design services. See his site for details.
4. For training in the US, Stuart Sutherland at
sutherland-hdl.com provides SVA training and a copy of our SystemVerilog Assertions Handbook, 2nd Edition book is handed out as part of the course.
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Ben Cohen (831) 345-1759
systemverilog.us/ ben at
ystemverilog.us * SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
* Component Design by Example, 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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Honored Contributor
