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Altera_Forum
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16 years ago

Using System Verilog Assertions

Hello, I've seen a few books on System Verilog Verification using assertions and was wondering if many people are using assertions in their FPGA development? My co-worker says it can be a lot of typi...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Thanks Ben! I had the same thoughts; it is just a matter of convincing my co-workers to adopt the practice of using assertions and other verification tools.

Thanks,

joe