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I think it actually saves typing :)
All the books that I've read also come to that conclusion.
But I'm not using it because Modelsim DE is too expensive for my company at the moment.
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Actually, assertions help in clarifying the requirements, the design review process, and the speed of debugging errors. In addition, it can provide information about coverage. So the time lost in typing is significantly gained in getting accuracy in the modeling of the design (because the assertions clarify the requirements), and in the verification of the design. See my paper on checkers at my site
systemverilog.us/DvCon2010 Even though the paper addresses IEEE 1800-2009 checkers, consider the assertions aspect of the design and the value of those assertions in the design and verification process.
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Ben Cohen (831) 345-1759
systemverilog.us/
* SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
* Component Design by Example, 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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Honored Contributor
