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Honored Contributor

15 years ago

Using System Verilog Assertions

Hello, I've seen a few books on System Verilog Verification using assertions and was wondering if many people are using assertions in their FPGA development? My co-worker says it can be a lot of typi...

Altera_Forum

Honored Contributor

15 years ago

I think it actually saves typing :)

All the books that I've read also come to that conclusion.

But I'm not using it because Modelsim DE is too expensive for my company at the moment.

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Using System Verilog Assertions

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