Honored Contributor
Honored ContributorI have noticed that in Altera Quartus we have the IP core tool which when opened for the SDRAM controller (did not find SRAM controller in the IP suite) actually opens up Qsys like GUI rather than the "Megawizard" type GUI that I am used to for creating a PLL or DSP multiplier.
I have read the "Introduction to Intel FPGA IP Cores". It states that there are different ways to simulate the cores, most of them use some sort of script. It then states: "1.8 Instantiating IP Cores in HDL Instantiate an IP core directly in your HDL code by calling the IP core name and declaring the IP core's parameters. This approach is similar to instantiating any other module, component, or subdesign. When instantiating an IP core in VHDL, you must include the associated libraries." Now I am shaking my head in disbelief. If I can just instantiate the IP core using its name and declaring the core's parameters, what is the point of so many files being generated? What also is the purpose of so many scripts? I do not see how they are being very helpful here. The main point that is not clear for this document is that it states: "When instantiating an IP core in VHDL, you must include the associated libraries." It does not explain how to know what the associated libraries are. This does not make any sense at all at this time. All I want to do is to get this SDRAM controller into my VHDL top level and simulate it
