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ArthurDent's avatar
ArthurDent
Icon for New Contributor rankNew Contributor
7 years ago
Solved

Using PHY with RMII interface on Cyclone V SoC

Hi I have added a second PHY to my board and connected it through the FPGA IO. I will use one of the HPS EMACs. The PHY is a 100Mb device with a RMII interface (not RGMII). What is the recommended...
  • Deshi_Intel's avatar
    Deshi_Intel
    7 years ago

    Hi,

    I checked HPS EMAC spec as per attachment.

    RMII is not supported in Cyclone V SOC. Yup, you need to write your own adaptor design if you insist to use it on CV.

    Alternatively, you can switch to Arria 10 SOC or Stratix 10 SOC that support RMII.

    Thanks.

    Regards,

    dlim

JOHI's avatar
JOHI
Icon for Contributor rankContributor
7 years ago

Hello,

There is FPGA IP that might do the job:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf

Tutorials are also available.

1. About This IP Core

The Intel FPGA Triple-Speed Ethernet IP core is a configurable intellectual property

(IP) core that complies with the IEEE 802.3 standard.

It incorporates a 10/100/1000-Mbps Ethernet media access controller (MAC) and an

optional 1000BASE-X/SGMII physical coding sublayer (PCS) with an embedded PMA

built with either on-chip transceiver I/Os or LVDS I/Os. When offered in MAC-only

mode, the IP connects with an external PHY chip using MII, GMII, or RGMII interface.

The IP core was tested and successfully validated by the University of New Hampshire

(UNH) interoperability.

Best Regards,

Johi.