using PFL in MAX II and MAX V

Hi, guys, recently, I am studying to use PFL in max cpld for FPP configuration of FPGA. I found that when I used PFL in max v 5m570zt100c5, the time requirement was not met (Fmax was less than 30mhz), while used in max ii epm570zt100c5, the time requirement was met( Fmax was higher than 50mhz). I think max v should be easier to meet the time requirement than max ii. Can anyone help figure out what's wrong? Thanks.