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Honored Contributor
Honored ContributorUsing Numonyx P33 TSOP for CIII AP Config
Hello, I would like some clarification on the Cyclone III AP configuration using the Numonyx P33 flash memory in the TSOP package. The Altera documentation seems to contradict itself. Her...
Altera_ForumHonored Contributor
Honored ContributorHey,
I have the exact same question. The Cyclone III datasheet sounds like it they say it will not work, but then defers the reader to the manufacturer datahsheet. So then I read the manufacturer datasheet and its not easily determined what the speed of the part is. From the Numonyx™ Axcell™ Embedded Memory (P30-65nm) datasheet timing parameters that are affected by TSOP package are: R1 tAVAV Read cycle time R2 tAVQV Address to output valid R3 tELQV CE# low to output valid R103 tVLQV ADV# low to output valid Additonal info seems like the master controller can adjust performance by the latency count? Latency count 3= Less than or equal to 40Mhz Latency count 4= Less than or equal to 52Mhz Since Altera provides hard IP and associated megafunctions, it would be nice if they get more specific and state which timing parameters exactly are key to determining why the TSOP would not work. Telling users to look at themanufacturer's datasheet is confusing since depending on the settings it can be 40Mhz or 52 Mhz. It would help people who are not familiar with using FLASH memory for FPGA programming to spell it out for newbies. Hope somebody can clarify the issue.
