Using Max10 ADC with PLL. Reset causes design to be unroutable.

Hello all,

I'm working with the Max10(10M08DAF256C8G) and I'm trying to use the internal ADCs. I'm driving the ADC clock from a PLL.

The problem I'm running into is I get the following error when I try to build the design:

Error (170084): Can't route signal "SlowADCInterface:SlowADC|ADCPLL:ADCPLL_inst|altpll:altpll_component|ADCPLL_altpll:auto_generated|wire_pll1_clk[0]" to atom "SlowADCInterface:SlowADC|Max10ADC:u0|Max10ADC_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|primitive_instance"
 

So it seems that Quartus doesn't think that it can route the design. The problem signal appears to be the clock output of the PLL given to the ADC clock input of the ADC module. Below are my instances for both of these.

   // ADC clock generation
    ADCPLL   ADCPLL_inst (
       .areset  ( Reset ),
       .inclk0  ( C50M ),
       .c0      ( clk_20mhz ),
       .locked  ( locked_adc )
       );
   
 
   // Max 10 ADC instance
   Max10ADC u0 (
      .adc_pll_clock_clk       (clk_20mhz),                 //  adc_pll_clock.clk
      .adc_pll_locked_export   (locked_adc),                // adc_pll_locked.export
      .clock_clk               (C50M),                      //          clock.clk
      .reset_sink_reset_n      (~Reset),                    //     reset_sink.reset_n
      .response_valid          (ADCRdStb),                  //       response.valid
      .response_channel        (ADCRdChannel),              //               .channel
      .response_data           (ADCRdData),                 //               .data
      .response_startofpacket  (),                          //               .startofpacket
      .response_endofpacket    (),                          //               .endofpacket
      .sequencer_csr_address   (sequencer_csr_address),     //  sequencer_csr.address
      .sequencer_csr_read      (sequencer_csr_read),        //               .read
      .sequencer_csr_write     (sequencer_csr_write),       //               .write
      .sequencer_csr_writedata (sequencer_csr_writedata),   //               .writedata
      .sequencer_csr_readdata  ()                           //               .readdata
   );

After messing with this for a while I found that if I invert the 'Reset' signal to the PLL the design will build correctly. Or if I feed it a constant 1 or 0.

Does anyone know why this might be happening?

Thank you,

Dylan