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However as the outputs of the ADC are nicely source synchronous and are accompanied by a dataclock and a frame-indicator , you can easily deserialise the ADC data channels with simple shiftregisters. Feed the inputs into a DDR-In block and then serialise the 2 bits in a 7-bit shiftregister each. assemble the 2 7-bit buses into a 14-bit bus and define the right moment to register it.
You need to do some work to constrain all this though.
I have done this for ADS527x and AD9222 octal ADCs, unfortunately my code is in AHDL (I do use VHDL nowadays).
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Hi josyb, I'm using an AD9252 pretty similar with AD9222. I have a question about what u said above.
Did ur AD output connect with the input of DDR-in block directly? When connecting directly, I got 2 Warnings like this.
Warning (176225): Can't pack node ad_ddio_in:inst_ad_ddio_in|altddio_in:ALTDDIO_IN_component|ddio_in_1di:auto_generated|input_cell_l to I/O pin
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
And the messages of Ignored Assignments are as follows.
Name: DDIO_INPUT_REGISTER
Ignored Entity:altddio_in
Ignored From:
Ignored To:input_cell_H
Ignored Value:HIGH
Ignored Source:Compiler or HDL Assignment
Name: DDIO_INPUT_REGISTER
Ignored Entity:altddio_in
Ignored From:
Ignored To:input_cell_L
Ignored Value:LOW
Ignored Source:Compiler or HDL Assignment
I don't know how to solve this problem. Could u give me some suggestions?
And, should the AD outputs connect some particular I/O pins? The FPGA I'm using is EP4CE115F29. Many thanks!
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