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Honored Contributor
Honored Contributorusing lvds
G´day !! I´m using an ADC with differential output (LVDS). It´s a device including 8 ADCs with Serial LVDS output. Data from each ADC is serialized and provided on a seperate channel. This seri...
Altera_ForumHonored Contributor
Honored ContributorI didn't yet observe the reported warning and don't know why it's generated in your design. May be it's due to the ad_in2_tmp wire signal.
Actually Cyclone IV uses LE registers for ddio_in, so the warning is irrelevant in any case. You should primarly look for succesful timing closure and first of all correct operation of actual hardware design.
