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Altera_Forum
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17 years ago

Using a PLL to synchronize two clocks

Hello, I have a 120 MHz external clock entering the FPGA (Stratix II). Part of the interface in the FPGA must work at the 120 MHz, but most of it (including a Nios CPU) works at 60 MHz. The 60 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Yes. They may not be down to the exact picosecond, but adding:

derive_clock_uncertainty

to your .sdc file(assuming you're targeting 65nm or newer devices) will add a little uncertainty to these transfers to account for this.

(If you're using the Classic Timing Analyzer or parts older than 65nm, the uncertainty is built into the model). For the record, a majority of designs do exactly what you're doing, so don't worry about it.