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Altera_Forum
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16 years ago

Using a PLL to synchronize two clocks

Hello, I have a 120 MHz external clock entering the FPGA (Stratix II). Part of the interface in the FPGA must work at the 120 MHz, but most of it (including a Nios CPU) works at 60 MHz. The 60 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

What's the source for these two clocks? Ideally you would have one clock come in and create both the 120 and 60 MHz clocks. Then everything works out(and TimeQuest will do what you want.) You don't even have to do Zero Delay Buffer.

It gets more confusing if they're two different clocks coming into the device, because you'll need to determine and phase difference and jitter between the external clocks and put that into your TimeQuest. If you explain the setup, there might be some more things to account for.