Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Using a PLL to synchronize two clocks

Hello, I have a 120 MHz external clock entering the FPGA (Stratix II). Part of the interface in the FPGA must work at the 120 MHz, but most of it (including a Nios CPU) works at 60 MHz. The 60 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

You can do it that way. Then use Timequest to ensure that the setup and holds are ok in the two domains. Ensure that the two clocks are in the same group so that Timequest analyses the transfers between the two domains. You may have to specify some multicycle transfers, but you can start without them and see what Timequest says.