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Altera_Forum
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16 years ago

User I/O conflict with DCLK (Cyclone 3)

I have custom board with EP3C5E144 used for educational purposes. Board contains EPCS16, SRAM and some other peripheral. I create NIOS system with program stored in EPCS (it was made in accorda...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I'm having this same issue, only I can't set the VCCIO to 2.5 - Quartus sees that I'm using an EPCS configuration device and forces the VCCIO back to 3.3, at which point I get the same thing. I'm using all of the available I/O pins on an EP3C40Q240, so I'm hoping there is a way to override this using an environment variable, and simply handle the issue logically (make sure access to the EPCS and the RAM are mutually exclusive) Is there any way to demote this to a warning?