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Altera_Forum
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16 years ago

User I/O conflict with DCLK (Cyclone 3)

I have custom board with EP3C5E144 used for educational purposes. Board contains EPCS16, SRAM and some other peripheral. I create NIOS system with program stored in EPCS (it was made in accorda...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I guess the restriction has been introduced by Altera because they observed crosstalk to DCLK. As long as the AS memory isn't operated while the RAM is active, it won't be needed however. The most simple workaround is to declare the respective I/O voltage incorrectly to 2.5V. I did this before in a design and never had to think about this issue.