Altera_Forum
Honored Contributor
Honored Contributoruser I/O clock
Hi Are there any drawbacks of using non-dedicated clock I/O pin to drive 50MHz clock for FPGA. I just read cyclone V manual and there is nothing wrote about it.
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Altera_ForumHonored Contributor
Honored ContributorIf it's a large fan-out clock, you'll probably want it on a global, so it will route from the regular I/O to the global. Not the end of the world and should work fine though. Note that your I/O delays will be different(longer Tcos, shorter Tsus). You won't be able to drive a PLL to shift the clock. (I actually, I don't remember if you can drive a PLL with an internal signal or not. Used to be illegal but may be legal on newer families. Try it if you think you might need it).
