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Altera_Forum
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18 years ago

Use Stratix II PLL to generate clock with deviations and jitter?

Hi, after reading the documentation about dynamic reconfiguration of Stratix II PLLs, altpll and altpll_reconfig, I believe that it is possible to use such PLL to generate a clock signal (e.g....
Altera_Forum's avatar
Altera_Forum
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18 years ago

Unfortunately, no. Implementing delay lines in FPGAs is not highly recommended because of the fluctuations you can see based on placement, process, voltage and temperature. If you must do this, you will need to manually place the delays to eliminate at least one of the four variables. The others, especially process, are beyond your control.