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Honored Contributor
Honored ContributorUse Stratix II PLL to generate clock with deviations and jitter?
Hi, after reading the documentation about dynamic reconfiguration of Stratix II PLLs, altpll and altpll_reconfig, I believe that it is possible to use such PLL to generate a clock signal (e.g....
Altera_ForumHonored Contributor
Honored ContributorBGG is right - for the first purpose, pll reconfiguration will work. For the other two it will not. You cannot change the phase or duty cycle quickly enough to allow you to emulate deterministic jitter.
