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Altera_Forum
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19 years ago

Use Stratix II PLL to generate clock with deviations and jitter?

Hi, after reading the documentation about dynamic reconfiguration of Stratix II PLLs, altpll and altpll_reconfig, I believe that it is possible to use such PLL to generate a clock signal (e.g....
Altera_Forum's avatar
Altera_Forum
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19 years ago

Hi, thanks for your reply.

> What did you have in mind?

Generally, the plan is to build a prototype for a data transmission system (somewhat similar to Ethernet 100FX: 125 MBps transmitted with NRZI encoding).

The prototypes are based on a ready-made board with Stratix II (the DBF2S30 from devboards.de). Not that we really need a Stratix, but because it features a fine modular concept and can carry up to 7 extension modules, which perfectly fit our requirements. A single board can simulate our whole system.

Now that we have the Stratix anyway and some unused PLLs in it, I thought it would be convenient to be able to use it as a source for stress tests... to prove that our transmission system can be pushed to the limits as per specification.

Kolja