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Altera_Forum
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18 years ago

Use Stratix II PLL to generate clock with deviations and jitter?

Hi, after reading the documentation about dynamic reconfiguration of Stratix II PLLs, altpll and altpll_reconfig, I believe that it is possible to use such PLL to generate a clock signal (e.g....
Altera_Forum's avatar
Altera_Forum
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18 years ago

Kolja:

I think your first purpose (slightly changing the freq.) is possible. Also, if you can't get the resolution you want using one PLL, maybe you can daisy-chain two--which is kind of an ugly solution, but possible.

As far as introducing jitter, I'm not sure how accurately you want to model jitter, but I think it will be really tough to do. Are you planning on changing the duty cycle randomly as fast as you can? What did you have in mind?

For the third purpose (phase mod.) you can probably do a rough emulation of this. If you can limit yourself to changing the parameters of the PLL that do not require you to re-sync you might be able to do this.

-B