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Honored Contributor
Honored ContributorUse spare memory in Active Serial configuration scheme
Hello, In my design I configure a Cyclone FPGA with a EPCS1 memory in the Active Serial scheme. I would like to use the free space of the memory for the application. Is there any document that tel...
Altera_ForumHonored Contributor
Honored ContributorHello again,
I have encountered another problem. In my circuit I wanted to use port 'Data0' (ECPS1's output) as an input to the FPGA to read the memory. When I try to assign an VHDL port to this pin Quartus Pin Planner gives me a message saying 'Value entered is not a valid location'. Is there any way to bypass this or is it impossible to use this pin for anything else but configuration?
