Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Use spare memory in Active Serial configuration scheme

Hello, In my design I configure a Cyclone FPGA with a EPCS1 memory in the Active Serial scheme. I would like to use the free space of the memory for the application. Is there any document that tel...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The FPGA image begins at address 0. If you use the programming files conversion tool (from Quartus' file menu) and generate a programming file for the EPCS1 from there it can generate a map file for you. It's a text file which says where all the flashed images are placed in the flash device. You can also use this tool to combine your FPGA image and your own custom data into a single programming file for the EPCS1.