Altera_Forum
Honored Contributor
9 years agoUse locked signal from PLL as reset
Hi guys,
I have some troubles by using a PLL in combination with a Qsys (HPS) system. On the arria10 development board, I try to increase the fpga clock (100MHz) with a PLL to 200MHz. For this, I instance a PLL from the IP Catalog. The 'refclk' is the 100MHz clock and the 'rst' signal is the fpga reset signal (from a button). I connect the outclk_0 (200MHz) to the Qsys component which includes a HPS and some other peripheral. I like to use the Avalon Bus in the 200MHz clock domain. After the synchronisation from the PLL 'locked' signal, I added the signal as reset to the Qsys component. Now, in the TimeQuest Analysis, I become a Recovery error on the reset signal. I saw, that Qsys added a "altera_reset_controller" block which include also a "altera_reset_synchronizer" block. In my designe, the timing violation is between this sync block ('altera_reset_synchronizer_int_chain_out' signal) and some Qsys component. Do somebody know why I receive this timing issue? By the way, when I use directly the external reset (from the button) the timing closure.. But in this case, I didn't checked the start up from the PLL... Thanks for your help and best regards, Moudi