Use locked signal from PLL as reset

Now I have a solution to my issue:

The problem was, that the external clock pin was close to the left bottom edge. In this case, a PLL close to the pin was selected.

Then, the clock output from the PLL and the synchronized reset signal was connected to a global clock network on the left bottom edge.

The other logic and devices from the HPS was located on the top edge from the FPGA. This distance (between top and bottom of the FPGA) is too large to close the timing...

When the PLL location is explicitly set to the center of the device, it works fine with 200MHz. I did a assignment for the specific PLL in the Assignment Editor to a specific location. Something like this:

To: PLLExample:u0|PLLExample_altera_iopll_160_khuhuhq:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst

Assignment Name: Location

Value: IOPLL_X78_Y114_N1

Cheers