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You can switch around any DQ groups. The PHY doesnt care and the user is invisible to it as the mix up on the way to the memory gets corrected on the way back.
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It would have made me think a bit harder if you had added that to your previous post.
I still think that swapping the DQs is not correct, because physically the received DQS doesn't match the sent DQx as both sets will be from different DDR2 chips whereof one may be 'slow' and the other 'fast' silicon. Writing will work fine as the timing depends on the FPGA only.
I'd rather suggest to try if e.g. John has connected say FPGA-DQS0 to SoDIMM-DQS1 (and FPGA-DQS1 to SoDIMM-DQS0) to swap The DQS pins on the FPGA side and rely on the fitter to route everything. So the DQS0 pin would end up in the DQ8..15 IO bank and DQS1 in the DQ0..7 IO bank.
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