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By design do you mean on the PCB? just swap the entire DQ group pinouts in the FPGA design.
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IMO that won't work. The HPCII PHY makes use of the DLsL to phase-shift the incoming DQS signals on read. So the ALTMEM_PHY may get confused on initialisation.
The best option to salvage the board is to write your own custom PHY using a PLL- generated phase to clock in the read data. At low frequencies this should be feasible, even easy at 125 MHz. If you feed the clock out on a free DPClk pin and route it back in (by forcing this in the Assignment Editor) the 'read clock' will track the silicon variation due to temperature and process quite close.
But you may best first try the HPCII as is - using the heat gun to see if it holds.
Honored Contributor
