Honored Contributor
Honored ContributorHi FvM,
Thank you, that is what I will attempt to do. I was concerned about phase but I can sort this out on the receiver. I had a couple of questions about driving the transceiver with a fractional PLL though if I could ask you? The first was if there was a specific way I had to instantiate the/a fractional PLL in order to use it? As I understand it the transceiver sets have dedicated clock networks: x1 for the shared serial clock and x6 for a shared set of clocks including the serial and the parallel. xN is a network that routes clocks between the transceiver sets. If I wish to drive a transceiver with an arbitrary clock I need to route this clock into this network somehow. Figure 2-9 on page 12 of the transceiver clocking documentation (http://www.altera.co.uk/literature/hb/stratix-v/stx5_52003.pd) it clearly shows an fPLL as a separate entity to the ATX PLL connecting to the x1 Clock Network, and I know the CMU PLLs are within each channel. Also, on Page 30 for an example it says: --- Quote Start --- "Six channel bonding is possible because the ATX PLL is used as a transmitter PLL instead of a channel PLL in the transceiver bank. Using the ATX PLL or fractional PLL allows you to use the channel PLLs of both channels 1 and 4 as CDRs to perform receiver operations." --- Quote End --- If I try and use the Transceiver PLL Megafunction however I can only select between CMU and ATX in the PLL Type of the PLL Reconfiguration section. I have tried connecting a regular fPLL to external clock of a Native PHY but receive an error: --- Quote Start --- "'[full instance name]' is not properly connected on the 'CLKCDRLOC' port." --- Quote End --- The Q&A page about it suggests I need to use a transceiver PLL: http://www.altera.co.uk/support/kdb/solutions/rd06172013_580.html With bonding, I can share x1 between the channels and each will generate the parallel clock locally with their own dividers. Or I can bond on x6 in which one generates the clocks which are used by all as shown on page 30 by Figure 2-26. Correct? I wonder if my setting the PHY to bond on x6 may cause this error, if the fPLL can only connect to x1? Could I just turn off bonding and rely on the divided clocks in each transceiver having low skew, simply by virtue of the transceiver hardware being implemented with very low tolerances? The second was about the interface clocking. From page 349 of the transceiver PHY user guide (http://www.altera.co.uk/literature/ug/xcvr_user_guide.pdf) it says: --- Quote Start --- You can also choose the tx_pll_refclk to transfer data, control, and status signals between the FPGA fabric and the transceiver channels. Because this reference clock is also the input to the TX PLL, it has the required 0 ppm difference with respect to tx_clkout. --- Quote End --- (When talking about tx_clkout as the reference for the data) If I provide a clock from a fractional PLL that is derived from my data clock, I can use the original to clock data into the transceiver correct? Also, dukzcry I looked but I don't have any images uploaded (?) (although I had some strange ones before ;))
