USB: FPGA to host communication - the same old story

Hey guys!

I have designed a simple SOPC system out of a JTAG URAT and a JTAG to Avalon Master Bridge module. I connected the Avalon Memory Mapped Master of the Bridge to the Avalon Memory Mapped Slave of the JTAG UART. Both modules are running with a 27,0 MHz clock and the r/w FIFO of the JTAG UART is 16 bytes deep. After generating I set the generated sopc_system.v as the Top-Level Entity. The system needs two inputs now: a clock input and a reset input. I have assigned the clock input to the 27Mhz clock on my DE1 Board (PIN_D12). However I can't reset the module, because I haven't assigned the reset input to a pin. I actually need another Top-Level Entity which controls the sopc_system!? Please correct me if I'm wrong!