Forum Discussion
Honored ContributorUSB: FPGA to host communication - the same old story
Hi altera forum users,
I know this was already podted many times and read all the topics about that, but nothing works for me. I want my PC as host and want to communicate with my FPGA design via USB. I have Terasic's famous DE1 Board and Quartus II 11.0sp1 Web Edition. I have tried many ways, but nothing worked for me: -using jtag_atlantic.dll doesn't work because I don't have vc++ -altera_jtag_to_avalon_mm_tutorial.pdf is a nice tutorial, but the communication based on quartus_stp, that's annoying! -image_download_demo doesn't work because I don't have vc++. I could use eclipse environment too, but I don't know how it works in eclipse. Please help me! I want to send/receive some bytes to/from the FPGA. It's really annoying that Altera's USB programming support is so bad.13 Replies
Altera_ForumIn case you do not plan to use VC++ you can still use the "system console (http://www.altera.com/literature/hb/qts/qts_qii53028.pdf)".
- Altera_Forum
You mean writing a TCL script and run it in the system Console? I don't have experience in writing tcl scripts, I don't even know how to run a script with parameters (args).
- Altera_Forum
In the console of the IDE (as well as the stand alone terminal application) can input keyboard commands and get results from your NIOS-2 on the DE1. For this you can configure your standard IO to use the JTAG-UART. If you write a command interpreter on your NIOS-2 can can control your NIOS in this way from your PC.
- Altera_Forum
You can download VC++ Express for free from Microsoft. It should have all the features you need.
BTW: did you forget an 's' in your user-name? For the non-german-speakers it means buy****, the forum S/W thinks it is quite rude as it doesn't display the translation :D - Altera_Forum
I donwloaded vc++ 2010 express, but the installer always fails on installing it. It doesn't say why it fails, that's really annoying. Now I'm installing some windows updates and hope that it works.
Yes I forgot the 's' in my username, but in german everyone knows what it means. Nice name, isn't it?:D - Altera_Forum--- Quote Start --- altera_jtag_to_avalon_mm_tutorial.pdf is a nice tutorial, but the communication based on quartus_stp, that's annoying! --- Quote End --- The tutorial shows how to use both quartus_stp and SystemConsole. The server can run on either of these interfaces, and then you can write a C client application. You can't really ask for more options than that! What is annoying is that Altera does not provide an API to call directly into a library for JTAG access. Cheers, Dave
- Altera_Forum
Now I have installed vc++ and I was able to compile a simple programm, which sends a "Hello" to the Board via jtag_atlantic.dll and USB Blaster.
Does anyone know a design example for my DE1 Board to receive the data and write it into a FIFO or whatever? If not, I think in SOPC it's not hard to create a JTAG module, isn't it?:unsure: Best regards, scheisekaufen - Altera_Forum
Hey guys!
I have designed a simple SOPC system out of a JTAG URAT and a JTAG to Avalon Master Bridge module. I connected the Avalon Memory Mapped Master of the Bridge to the Avalon Memory Mapped Slave of the JTAG UART. Both modules are running with a 27,0 MHz clock and the r/w FIFO of the JTAG UART is 16 bytes deep. After generating I set the generated sopc_system.v as the Top-Level Entity. The system needs two inputs now: a clock input and a reset input. I have assigned the clock input to the 27Mhz clock on my DE1 Board (PIN_D12). However I can't reset the module, because I haven't assigned the reset input to a pin. I actually need another Top-Level Entity which controls the sopc_system!? Please correct me if I'm wrong! - Altera_Forum--- Quote Start --- Yes I forgot the 's' in my username, but in german everyone knows what it means. Nice name, isn't it?:D --- Quote End --- [critisim = on] Nice Name? - Depends on the point of view! To be honest, I usually kick out people with such "intelligent names" from forums I have to moderate! [critisim = off] [advisory mode = on] I guess you might have more acceptance and maybe also more support from people, by selecting a name with more sensibility. [advisory mode = off] Did you progress with your tries to communicate with the FPGA-board? I started to establish a discussion regarding UDP , maybe you want to participate?
- Altera_Forum--- Quote Start --- critisim = on] Nice Name? - Depends on the point of view! To be honest, I usually kick out people with such "intelligent names" from forums I have to moderate! [critisim = off] [advisory mode = on] I guess you might have more acceptance and maybe also more support from people, by selecting a name with more sensibility. [advisory mode = off] --- Quote End --- OK, I understand your point of view. However, let's concentrate a little bit more on the topic here please! --- Quote Start --- Did you progress with your tries to communicate with the FPGA-board? --- Quote End --- Look at the my post above yours. This is still my current progress. --- Quote Start --- I started to establish a discussion regarding UDP , maybe you want to participate? --- Quote End --- OK, please post the link!
