URGENT: Peripheral to Memory DMA Transaction

Good to see you're making progress :-)

Yes, the fifo might overrun if you feed it too much data, or underrun if it is empty.

I have seen strange behaviour when writing to a full fifo or reading from an empty one; the behaviour in such case is not defined.

Normally, you would read the usedw through another register, and estimate how much data you can read or write in your DMA. Also, one normally connects full/empty to an interrupt line to tell you when you need to react on it. The logic in your periphereal normally also needs to stop stransmission when the fifo is full resp. empty.

But for testing it is sufficient to just use it so.

In my design, I use a comparator with a threshold register, so I get an interrupt when the fifo is more or less half full.