Forum Discussion
Altera_Forum
Honored Contributor
15 years agoi have done configuring my scFIFO. i exclude the signal full, empty and usedw, but i did enable the circuitry protection. is it ok? FIFO block has 4 inputs (clk, data, rdreq and wrreq) and 1 output (q). is it ok? thanks!
P/S: data is 32 bit and the deep the FIFO should be is 131072 words (256K). Is it ok? Besides, I have one uncertainty here. The FIFO, will it be full? It is a buffer, once it is full with data, will it override itself with new data, or i have to override or reset it manually?