URGENT: Peripheral to Memory DMA Transaction

now i think i understand... correct me if i am wrong:

i connect two FIFO to x and y respectively, then 1 FIFO to result. the former 2 FIFO are connected to avalon bus. and the later FIFO is connected to DMA. am i right?

when i see the pdf regarding FIFO, in the sample design, they use write control logic and read control logic, where FIFO is in between both logic. do i need write and read control logic in this context?