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emrahener's avatar
emrahener
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3 years ago

Unused Agilex F Tiles and recovered clk output.

Hi, We are using AGIB027R31B2E2V on our digital board design. We are using FHT13C but not using FHT13A. Pin Connection guideline says Tie to GND if there is no FHT channel used for the followi...
emrahener's avatar
emrahener
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3 years ago

Hi Aqid,

Thanks for the replies. There is only one open point in the ticket regarding the recovery clk. For the two other issues I have no further questions.

`Another question is on recovery clock output from F tiles. Is there a specific reason to have them as output from clk pins instead of routing them through fabric ? This is a question to minimize test connector cnt on out design If we can route the recovery clk through fabric I will mux recovery clk from multiple links inside FPGA and observe them on a single external connector. Is there a rule for their pin assignment when used for links with more than 4 differential pairs? Is it at the same frequency with the data rate or with the reference clk input? Is it LVDS?`

Kind Regards

Emrah ENER