Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

undesired sidebands on Cyclone IV E PLL output

I am using a PLL in a Cyclone IV E. I have a 20 MHz oscillator connected to a clock-input pin. I am trying to get 200 MHz as the output. For the design, I am using only an ALTPLL megafunction bloc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

--- Quote Start ---

Glad that you solved your problem. But I also take it that you used a switcher for the 2.5V due to the 22kHz oscillations, and because of this an LDO is a good conservative design approach. Knowing the sensitivity of the PLL's is why I use LDO + LC filters, with large, medium tantalum caps and also a ceramic cap. Best, James

--- Quote End ---

This is the approach I have taken too, but be aware that for many LDO's the power supply rejection ratio (for noise) drops off massively with frequency so high frequency switcher noise can get through.

I had a good app note about this that recommended ferrite beads _around_ the output wires (I have used ferrites in line with varying values of caps). Unfortunately I can't find it right now.

Nial.