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Altera_Forum
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11 years ago

Understand and solve setup violation in dual domain clock

Hello all, I have a project where I have two clock: - 50 MHz oscillator for NIOS synthetized on FPGA - 60 MHz oscillator for USB (from UM232H module) used in a custom component attached w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Deleting ADBUS from signaltap seem to remove violation. Are so hard to observe bidirectional pin?