Understand and solve setup violation in dual domain clock

Hello all,

I have a project where I have two clock:

- 50 MHz oscillator for NIOS synthetized on FPGA

- 60 MHz oscillator for USB (from UM232H module) used in a custom component attached wtih QSys to NIOS

QSys automatically handle cross-domain transfers of signals.

I wat to see signals that come and go into USB module with signaltap so I have multiplied by 2 (to 120 MHz) USB clock with a PLL and attached it to SignalTap.

Timing requirements are not met because I have ADBUS signals (bidirectional DATA signals for USB) that violate setup timing by -0.684ns

If I report Timing Closure Reccomendations with TimeQuest I get:

--- Quote Start ---

Register the partition boundaries for the path from pin_ft232h_ADBUS[5] to sld_signaltap:aut...rigger_in_reg[5]

Issue: Cross-partition Paths

From: pin_ft232h_ADBUS[5]

To: sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[5]

TimeQuest analysis: report timing

Partitions that should be merged:

Top -> sld_signaltap:auto_signaltap_0

--- Quote End ---

What can I do? Attached Timequest details