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Altera_Forum
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12 years ago

Unaligned access when trying to reach AXI-LW from U-Boot

Hello, I have a QSYS system, including some Avalon-MM peripherials connected to the AXI-LW interface of the HPS. For testing purposes I tried to read their registers from the serial consol...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Dunno - A nios system wouldn't be able to generate an Avalon address of ff200000 without going through the mmu (because the top bit requests 'cache bypass').

Whatever memory uboot is running from has a virtual address ending at 40000000 - might give a hint about whether it runs with the mmu enabled or not. I suspect the arm cpu runs like a 'sick pig' without the i-cache enabled, but it is a long time since I've done anything with an arm cpu and I can't remember whether you have to enable the mmu in order to enable the caches.