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Altera_Forum
Honored Contributor
Honored ContributorUnable to see the falling edge pulse in Quartus simulator
A very short falling edge pulse will be generated in the test_out output port during rtl simulation in modelsim ase 6.5b. However, I cannot see this short pulse in Quartus II simulator during functio...
Altera_ForumHonored Contributor
Honored ContributorUsing a CPLD makes the difference, because it apparently utilizes a different synthesis tool. You have to set "IGNORE LCELL BUFFERS" to off additionally to keep logic cells, then you get the intended result.
http://www.alteraforum.com/forum/showthread.php?t=22110 By the way, checking the previous synthesis result at the gatelevel with the netlist viewer tool easily reveals, why it can't work. It's quite different from the FPGA netlist.
