Unable to meet timing requirements for 180 MHz Source-Synch. DDR Interface due to PLL uncertainty

Hi all,

A MWE QPF is attached. It features two ADCs (one single channel, one dual channel) with a total of 20 DDR LVDS outputs + 2 LVDS clocks. Three clocks enter the FPGA: the two clockouts from the ADC as well as the encode clock that is will (externally) drive the ADCs.

Originally I planned on using the 5CSXFC6C6U23C7 chip until I found out that some of the differential receiver pairs introduce additional delay due to the HMC and should not be used for fast signals. Therefore I will propably change to the 5CSEBA4U23I7 chip which resulted in additional phaenomena:

- Initially, the ADC clocks were connected to the CLK0 / CLK3 and the encode clock to CLK2. With these assignments, the fitter fails for the SE chip (but not the SX chip) because it cannot place one of the PLLs. When changing the input of the encode clock to CLK6, both chips compile fine (and the timing for the SX is improved compared to using CLK2 as input).

- With the 5CSEBA4U23I7 chip I can just meet the timing requirements with the PLL in place, with the 5CSXFC6C6U23C7 chip I still cannot because the "data valid window" becomes negative. Could this be due to the HMC resources which are present in the SX but not in the SE chip?

For both chips however, omitting the PLL leads to significantly improved margings which brings me back to the original question: Is there a mistake in my configuration or is it true that the PLLs add so much uncertainty that a shift (if necessary) in my case should be done at the ADC?

Thank you in advance for any help!