Occasional Contributor
Regular ContributorHi,
Do you have the design in Platform Designer? If so, did you get any errors when generating the HDL in Platform Designer?
What is your device part number? Below is the example of the part list:
https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html?1
Also, could you check below KDBs to see if it might solve your issue:
Occasional ContributorHi,
Parts of the design are in platform designer. I don't get any errors when generating HDL from platform designer nor the IP parameter editor. I've got some warnings related to PCIe tile but they don't seam to be related to the problem.
Yet, for measure of good cause I've attached them below:
Warning: intel_pcie_ptile_ast_0.intel_ptile_io_pll_250: Able to implement PLL - Actual VCO frequency differs from requested setting Warning: intel_pcie_ptile_ast_0.intel_ptile_io_pll_250: Able to implement PLL - Actual VCO frequency differs from requested setting
The exact part number is
AGFB014R24A2E3VR0The linked KDB articles do not seam to be related. Even if I disable all pin constraints but one I still get these error messages so it can't be the ussage of the same IO for two different functions. Furthermore, if i disable all constraints it will place the peripheral pins at random and quartus also placed the pins in exactly the way I wanted them to be once. I can't rely on rerunning the fitter until it randomly places the pins in correct order though as this would make effective work kinda impossible.
