uart communications

hmm, ok, thanks for the clock info, I've corrected it to:

if (waiter == 13'b1010001011000) //9600 times a second (aprox)

I'm using:

http://www.maplin.co.uk/module.aspx?moduleno=97733&doy=12m2

and

http://www.maplin.co.uk/module.aspx?moduleno=97872&doy=12m2

and its not working. So if your sure it can be done with that cable, then there must be something up with my timing code, as I have the UART_TXD light flashing as it should.

Any more ideas about what could be wrong. I'm running hyperterminal set to 9600bps, 1 stop bit, no parity bit, no flow control. Listening on port COM1. And when I switch switch 0 on the fpga hyperterminal picks up nothing.

my latest code is:

module test5(input  CLOCK_50,
	output  LEDR,
	output UART_TXD,
	input  UART_RXD,
	input  SW
	);
	
	reg  waiter = 13'b0000000000000; //counter to reduce clock rate
	//reg  waiter = 13'b0000000000000; //counter to reduce clock rate
	reg  state = 4'b0000; //current state. 0 = start bit, 1-8 = data bits, 9 = stop bit, other = ended
	reg data = 1'b1; //start high = idle state
	reg clk_new = 0; //changes the state of an led every time a bit is sent
	
	reg  origData = 16'b0101001100111001; //S 9 in ascii
	reg  currData;
	reg started = 0;
	assign LEDR = data; //led outputs current data bit
	assign LEDR = SW; //led outputs status of a switch
	assign LEDR = clk_new; //led shows when new bit is sent
	assign UART_TXD = !data; //assert the transmit wire to the data bit
	
	always @(posedge CLOCK_50) //every clock tick
	begin
		//if (waiter == 27'b111111111111111111111111111) //1/2 times a second
		if (waiter == 13'b1010001011000) //9600 times a second (aprox)
		begin
			if (started == 0) //have we not started yet?
			begin
				if (SW) //start if switch 0 is high
				begin
					started = 1;
					currData = origData; //set the current data register to be the original data register
				end
			end
			else //we have started
			begin
				clk_new = !clk_new; //change clock led
				waiter = 13'b0000000000000; //reset counter
				if (currData == 16'b0000000000000000 && state == 4'h0) //end of transmit
				begin
					data = 1'b1; //idle bit
					if (!SW) //if switch 0 is low, then reset to not started
					begin
						started = 1'b0;
					end
				end
				else
				begin				
					if (state == 4'h0) //start bit
					begin
						data = 1'b0;			
					end
					else if(state == 4'h9) //stop bit
					begin
						data = 1'b1;
					end
					else if(state < 4'h9) //data bits
					begin
						data = (currData & 1'b1); //get first bit
						currData = currData >> 1; //right shift, so as first bit is the next bit to send
					end
						
					if (state == 4'h9) //update state
					begin
						state = 4'h0;
					end
					else
					begin
						state = state + 1'b1;
					end
				end //end data left to transmit
			end //end started == 1
		end //end if (waiter == ...)
		waiter = waiter + 1'b1;  //inc waiter
	end //end always @...
	
endmodule