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Altera_Forum's avatar
Altera_Forum
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18 years ago

uart communications

Hey, I'm doing a project involving the DE2 FPGA, where I need to communicate with a pc via a serial interface. I have checked the pin assignments file and noticed there are only 2 pins associated wit...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello,

I could verify, that the module doesn't operate fully correct:

1. RS232 data should be LSB first

2. If you have a 50 MHz clock, the baudrate is proabably too inaccurate. Actual Baudrate is 50e6/(0x1555+1) = 9154 Baud (- 4,6 %). By the way, Verilog knows also hex and decimal constants, e. g. 13'd5207.

Operation would be much easier using a shiftregister for the UART.

Regards,

Frank