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Honored Contributor
Honored Contributortwo avalon buses in one FPGA tutorial?
Hi, I know it is possible to have multiple avalon buses in one FPGA, but how can I do it? somebody know where I can found a tutorial? Thanks, Sam
Altera_ForumHonored Contributor
Honored ContributorAFAIK the SRAM and the SDRAM don't share any pins, but the SRAM and the CFI flash do, on the kits that have a parallel flash.
If you use only one Nios CPU it has only one data master, so it will share it between the two memories anyway. Why exactly do you absolutely want 2 buses?
